1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor device having a self-aligned contact structure and a manufacturing method thereof.
2. Description of the Background Art
As a degree of integration of a semiconductor device increases, a width of a wiring decreases and a space between the wirings also decreases. When a contact hole connecting upper and lower wirings is formed, the contact hole must be formed with a hole diameter smaller than a width of the space between adjacent wirings. That is, a hole diameter C of the contact hole required for design rules of 0.25 μm for the space between the adjacent wirings will be C≦0.25−f(α,β) μm, considering overlay accuracy (=α) and dimensional accuracy (=β) in a photolithographic processing step, which exceeds a limit of size reduction depending on a wavelength of a light source of an exposure system.
To solve the above-described problem, a self-aligned contact technique has been used for manufacturing the semiconductor device of the 0.25 μm rules.
In a DRAM (Dynamic Random Access Memory), the self-aligned contact technique is mostly used for a bit line contact and a storage node contact formed between word lines within a memory cell array. The most important point is to connect the bit line or the storage node to a source/drain region of a memory cell transistor with a resistance as low as possible without making an electrical short circuit with a word line.
A manufacturing method of a background art using the self-aligned contact will now be described.
An active region electrically isolated by a silicon oxide film deposited on an element isolation region is formed. A gate electrode to be a word line of the DRAM is formed on a gate insulation film formed in the active region. The gate electrode and a nitride film hard mask thereon are covered with an etching resistance film formed by a nitride film similar to the hard mask. The gate electrode is then covered with a silicon oxide film including impurities of boron and phosphorus, and thereafter, a surface of the silicon oxide film is planarized.
Then, the silicon oxide film including impurities of boron and phosphorus is selectively etched to expose the etching resistance film. The exposed etching resistance film is etched to form a contact hole exposing a pair of source/drain regions. A polycrystal silicon film doped with an n type impurity is form to contact with each of the exposed pair of source/drain regions. As a result, a bit line contact electrically connecting a bit line with one of the source/drain regions, and a storage node contact electrically connecting a storage node with the other of the source/drain regions are formed. In this step, the bit line or the storage node can be connected to the source/drain region while the source/drain region and the gate electrode are electrically insulated.
A manufacturing method using the self-aligned contact is disclosed in, for example, Japanese Patent Laying-Open No. 2000-353793.
For design rules of at most 0.13 μm having an extremely narrow space between gate electrodes, a problem of an “aperture defect”, or a problem of difficulty in ensuring a process tolerance of an electrical “short” of the gate electrode and the polycrystal silicon film occurs in the above-described background art because of a microloading effect caused by a difference in hole diameters of the bit line contact and the storage node contact. More specific descriptions are given below.
Proceeding of etching of the contact hole having a smaller hole diameter becomes hard by the microloading effect. Therefore, when the etching is performed in a condition suitable for the contact hole having a larger hole diameter, the etching proceeds insufficiently in the contact hole of the smaller hole diameter, resulting in the “aperture defect”.
On the other hand, when the etching is performed in a condition suitable for the contact hole of the smaller hole diameter, the etching excessively proceeds in the contact hole of the larger hole diameter. As a result, the etching resistance film formed with a silicon nitride film is removed substantially in addition to the silicon oxide film, and the gate electrode is exposed. If the polycrystal silicon film is formed within the contact hole in this situation, the electrical “short” of the gate electrode and the polycrystal silicon film is generated. To avoid such “short”, thickness of the etching resistance film must be increased, an thus decreasing of the thickness of the etching resistance film becomes difficult.
Formation of a photoresist pattern by scaling of a pattern pitch of the storage node contact and the bit line contact is also difficult. A problem is that, a contact resistance is increased when the hole diameter is small, while a hole coupling (an electrical short) will be generated when the diameter is increased.
In particular, as a channel width of the memory cell transistor in the DRAM is decreased and current drivability is also decreased, the contact resistance must be made equal to or lower than that in a previous generation despite the size reduction to attain a stable cell operation. Therefore, a breakthrough in the conventional technique is needed.